Jobs
Cognitive Electronics is looking for hardware and software engineers who want to be a part of building something great. Cognitive is a young growing company with exciting technology that is poised to make a big splash in some of the most important markets in tech. But, if you are an engineer with a deep knowledge of ASIC design, verification, complier design, kernel engineering, device drivers or test engineering, none of what we at Cognitive are looking to do is possible without you. We are looking for engineers that not only have the skills, but also the desire to be a part of a small team that shakes up the industry. If you are that person, we are looking for you, are you looking for us? Contact us at jobs@cognitive-electronics.com
Title: Digital Design Engineer
Responsibilities: The Digital Design Engineer will design, document, develop and verify digital hardware components to be integrated into the Cognitive Electronics processor, an innovative, low-power ASIC architecture for Big Data applications. He or she will code SystemVerilog and Verilog modules, testbenches and functional coverage constraints. Custom processing datapath and network-on-chip logic will be optimized for power, target leading edge semiconductor process technology and interface with high performance I/O and memory IP.
The Digital Design Engineer will be responsible for all aspects of front-end ASIC design, including:
- Architecture definition
- Digital design
- Implementation in Verilog, System Verilog
- Verification with UVM
- UVM environment development
- Timing constraint definition and debug
- IP integration
- Logic synthesis
Reporting Structure: The Digital Design Engineer will report to the Vice President of Product. He or she will also work closely with leadership and members of the ASIC Engineering team to achieve the most cost and energy efficient implementation of the Cognitive processor in the shortest possible time.
Required Experience: BSEE or equivalent with 5 years of digital design experience coding RTL for ASICs, processors, coprocessors or similar chips. Experience with low-power SoC design, Verilog, SystemVerilog, timing constraints and constrained random verification, UVM, VMM or OVM. Knowledge of Tcl, Perl and/or other scripting languages.
Desired Experience: MSEE or equivalent plus 5 years of experience in digital ASIC and/or microprocessor design. Experience with UPF, multi-voltage implementation and verification flows. Knowledge of embedded DRAM and PCIe Endpoint IP. Familiarity with ASIC synthesis tools. Functional verification experience including UVM environment development, functional coverage, SystemVerilog assertions, code coverage and development of module testbenches from scratch. Makefile development a plus.
Compensation: A market competitive package, including stock options.
Title: Principal Compiler Engineer
Responsibilities: The Principal Compiler Engineer will lead the effort to develop the Cognitive Electronics compilers, libraries and tools, in particular highly optimized compiler back-ends for GCC and/or LLVM targeted to the Cognitive processor. This is a hands-on position that will require driving the compiler architecture, design and development process in addition to providing leadership to the Software Engineering team.
Reporting Structure: The Principal Compiler Engineer will report to the Vice President of Product. He or she will lead development of the Cognitive Electronics compilers, libraries and tools while working closely with the rest of the Software Engineering team as well as with the Chief Architect.
Required Experience: BSCS/EE or equivalent and 7 years experience in compiler development and optimization in GCC, LLVM or similar compilers, with at least two years in a leadership role. Expert in UNIX/Linux software development environments and tools such as C, C++, FORTRAN, Java, Python, Eclipse and Subversion.
Desired Experience: MSCS/EE or equivalent plus 10 years of experience leading the design and implementation of compiler back-ends and/or optimizers for sophisticated high-performance UNIX/Linux computing environments. Specific knowledge of GCC and/or LLVM and experience with high-performance computing systems utilizing heavily multi-threaded RISC and/or GPGPU processor architectures highly desired. Knowledge of MPI, OpenMP, MapReduce, UPC/PGAS or similar desired. Experience with development in UNIX/Linux environments; knowledge of Windows and/or Mac OS X a plus.
Compensation: A market competitive package, including stock options.
Title: Hardware Test Engineer
Responsibilities: The Hardware Test Engineer will be responsible for test development, execution and analysis of Cognitive Electronics ASICs, boards and systems. The Hardware Test Engineer will work closely with leadership and members of the ASIC Engineering, System Engineering and Software Engineering teams to achieve the highest quality, most cost-effective implementation of Cognitive chips, boards and systems in the shortest possible time.
Reporting Structure: The Hardware Test Engineer will report to the Vice President of Product. He or she will work closely with the other members of the ASIC Engineering team, as well as with the System Engineering team, responsible for the creation of Cognitive boards and systems, and with the Software Engineering team, responsible for the creation of Cognitive operating systems, compilers, libraries and tools.
Required Experience: BSEE or equivalent with 3 years of experience developing, executing and analyzing hardware tests for systems containing new ASICs, processors, coprocessors or similar chips. Experience with at least one of RISC, GPGPU or x86 architectures. Knowledge of at least one Linux scripting language. Detailed understanding of and experience with hardware test tools, fixtures and methodologies.
Desired Experience: MSEE or equivalent plus 5 years of experience developing, executing and analyzing hardware tests for systems containing complex high-performance processors, coprocessors or similar chips. Strong knowledge of C, C++, Java, Python, Perl, and/or other scripting languages and test frameworks. Test engineer on a team that successfully implemented a system containing a new chip that shipped on time and on budget. Experience developing, executing and analyzing hardware testing for high-performance computing systems, heavily multi-threaded processors and/or coprocessors using RISC, x86 and/or GPGPU architectures highly desired. Understanding of hardware interactions in complex, large-scale high-performance computing systems preferred. Knowledge of HDL and design systems such as Cadence and Synopsys desired. Experience with testing in UNIX/Linux environment; knowledge of Windows and/or Mac OS X a plus.
Compensation: A market competitive package, including stock options.
Title: Kernel/Drivers Engineer
Responsibilities: The Kernel/Drivers Engineer will be responsible for leading the development of the Cognitive Electronics Linux kernel and drivers.
Reporting Structure: The Kernel/Drivers Engineer will report to the Vice President of Product. He or she will design and develop the Cognitive Electronics processor driver and any necessary changes to the Linux kernel. He or she will also be a key member of the Software Engineering team, responsible for the creation of Cognitive compilers, libraries and tools in addition to the kernel and drivers.
Required Experience: BSCS/EE or equivalent and 5 years experience with UNIX/Linux kernel and driver development in a high-performance computing or enterprise-class environment. Strong knowledge of C and/or C++. Experienced in use of software development environments and tools such as Python, Eclipse and Subversion.
Desired Experience: MSCS/EE or equivalent plus 7 years of experience designing and implementing kernel modifications and device drivers for high-performance Linux computing environments, particularly drivers for coprocessors or GPGPUs. Strong ties to Linux community; has had code accepted to kernel.org. Experience with high-performance computing systems, heavily multi-threaded processors and RISC, GPGPU and/or x86 architectures highly desired. Familiarity with MPI, OpenMP, MapReduce, PGAS or similar desired. Knowledge of Mac OS X and/or Windows a plus.
Compensation: A market competitive package, including stock options.
Title: Software Test Engineer
Responsibilities: The Software Test Engineer will be responsible for test development, execution and analysis of Cognitive Electronics software including operating systems, compilers, tools and libraries. The Software Test Engineer will work closely with leadership and members of the Software Engineering team to achieve the highest quality, most cost-effective implementation of Cognitive software, chips, boards and systems in the shortest possible time.
Reporting Structure: The Software Test Engineer will report to the Vice President of Product. He or she will work closely with the other members of the Software Engineering team, as well as with the System Engineering team, responsible for the creation of Cognitive boards and systems, and with the ASIC Engineering team, responsible for the creation of Cognitive chips.
Required Experience: BSEE or equivalent plus 2 years of experience developing, executing and analyzing software tests in a Linux and/or UNIX environment. Experience with at least one of RISC, GPGPU or x86 architectures. Knowledge of at least two of C, C++, Python, Java or Perl. Understanding of software test tools and methodologies. Familiarity with software development tools and methodologies such as Eclipse and Subversion.
Desired Experience: MSEE or equivalent plus 4 years of experience developing, executing and analyzing software tests in a high-performance computing and/or enterprise environment, preferably including heavily multi-threaded processors and/or coprocessors using RISC, x86 and/or GPGPU architectures. Strong knowledge of C, C++, Java, Python, Perl, and/or other scripting languages and test frameworks. Test engineer on a team that successfully shipped a new system on time and on budget. Understanding of hardware/software interactions in complex, large-scale computing systems preferred. Experience with testing in UNIX/Linux and/or Mac OS X environments; knowledge of Windows a plus.
Compensation: A market competitive package, including stock options.
Title: Senior Verification Engineer
Responsibilities: The Senior Verification Engineer will be responsible for leading the design and implementation verification of the Cognitive Electronics processor. The Senior Verification Engineer will work closely with leadership and members of the ASIC Engineering team to achieve the most cost and energy efficient implementation of the Cognitive processor in the shortest possible time. This is a hands-on position that will require the Senior Verification Engineer to be directly involved in the design, development and verification process.
Reporting Structure: The Senior Verification Engineer will report to the Vice President of Product. He or she will work closely with the ASIC Architect, ASIC Designers and other members of the ASIC Engineering team, as well as with the System Engineering team, responsible for the creation of Cognitive boards and systems, and with the Software Engineering team, responsible for the creation of Cognitive operating systems, compilers, libraries and tools.
Required Experience: BSEE or equivalent with 5 years of experience verifying ASICs, processors, coprocessors or similar chips. Experience with at least one of RISC, GPGPU or x86 architectures. Detailed understanding of and experience with verification tools and methodologies as well as HDL and design systems such as Cadence and Synopsys.
Desired Experience: MSEE or equivalent plus 7 years of experience verifying complex high-performance processors, coprocessors or similar chips. Experience verifying chips for high-performance computing systems, heavily multi-threaded processors and/or coprocessors using RISC, x86 and/or GPGPU architectures highly desired. Lead verification engineer on a team that successfully implemented a new chip that shipped on time and on budget. Knowledge of Infiniband, PCI Express or other system interconnects and networking technologies a plus. Understanding of hardware interactions in complex, large-scale high-performance computing systems preferred.
Compensation: A market competitive package, including stock options.
Title: Verification Engineer
Responsibilities: The Verification Engineer will be responsible for design and implementation verification of the Cognitive Electronics processor. The Verification Engineer will work closely with leadership and members of the ASIC Engineering team to achieve the most cost and energy efficient implementation of the Cognitive processor in the shortest possible time. This is a hands-on position that will require the Verification Engineer to be directly involved in the design, development and verification process.
Reporting Structure: The Verification Engineer will report to the Vice President of Product. He or she will work closely with the Senior Verification Engineer and other members of the ASIC Engineering team, as well as with the System Engineering team, responsible for the creation of Cognitive boards and systems, and with the Software Engineering team, responsible for the creation of Cognitive operating systems, compilers, libraries and tools.
Required Experience: BSEE or equivalent with 2 years of experience verifying ASICs, processors, coprocessors or similar chips. Experience with at least one of RISC, GPGPU or x86 architectures. Detailed understanding of and experience with verification tools and methodologies as well as HDL and design systems such as Cadence and Synopsys.
Desired Experience: MSEE or equivalent plus 3 years of experience verifying complex high-performance processors, coprocessors or similar chips. Experience verifying chips for high-performance computing systems, heavily multi-threaded processors and/or coprocessors using RISC, x86 and/or GPGPU architectures highly desired. Verification engineer on a team that successfully implemented a new chip that shipped on time and on budget. Knowledge of Infiniband, PCI Express or other system interconnects and networking technologies a plus. Understanding of hardware interactions in complex, large-scale high-performance computing systems preferred.
Compensation: A market competitive package, including stock options.